This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
A current sense amplifier is often employed in a non-volatile memory device, such as a flash memory, to read out the state of a memory cell from within a large array of such cells by comparing the amount of current flowing through the memory cell to a reference value.
In systems using programmable devices, such as programmable logic devices (PLDs) and/or field-programmable gate arrays (FPGAs), to monitor and/or control other system components, the programmable devices must be properly configured before they can start operating the other system components. Configuring a programmable device typically occurs by down-loading (reading) configuration data from non-volatile memory.
When a programmable device is initially turned on (i.e., powered up), a supply ramp-up phase occurs in which the power supply voltage (e.g., Vcc) of the programmable device increases over time from zero to its normal operating level (e.g., 1.2V). Providing a memory device that can operate at relatively low voltages (i.e., below the normal operating level) can enable the programmable device to be configured relatively quickly (i.e., before the power supply voltage reaches its normal operating level), thereby reducing the time that it takes for the programmable device to start operating. Unfortunately, typical flash memory technology imposes certain constraints that make this difficult to achieve.
FIGS. 1A-C show schematic circuit diagrams of three different conventional configurations for sensing non-volatile memories. FIG. 1A shows a reference-biased trans-impedance sense amplifier, while FIG. 1B shows an inverter-biased trans-impedance sense amplifier. As shown in the figures, both of these configurations involve a bias reference generator and a trans-impedance amplifier employing a common-gate NMOS (N-type metal oxide semiconductor) transistor as the amplifying device (i.e., transistor i92 in FIG. 1A and transistor i54 in FIG. 1B). The transistor source serves as the input connection from a bit line of the memory array, and the transistor drain, via a skewed inverter, serves as the output of the amplifier (i.e., sout1 in FIG. 1A and sout2 in FIG. 1B). The drain is pulled to the positive power supply rail (i.e., vpwr in FIGS. 1A and 1B) through a fixed current source (i.e., transistor i96 in FIG. 1A and transistor i45 in FIG. 1B). These configurations pull a selected memory bit line toward a fixed voltage, while converting the bit-line current flow into a voltage output to drive a voltage detector (not shown) that determines whether the bit line corresponds to a logic 1 or a logic 0.
The configuration of FIG. 1A is small and power efficient and can maintain the memory cells at a fixed voltage that is largely independent of power supply voltage.
The configuration of FIG. 1B provides higher gain and simpler reference generation, but uses more power and allows the memory cell voltage to vary with the power supply voltage (around the switch point of the feedback inverter formed by transistors i56 and i57), making it unsuitable for many flash technologies. One significant problem with the prior-art configurations of FIGS. 1A and 1B is their requirement for substantial power supply voltage headroom to keep the analog trans-impedance amplifier stage biased, and to produce enough voltage swing for dependable conversion to digital levels. Examples of such configurations commonly require power supply voltage levels greater than 1.8V to operate properly. See, e.g., Shigeru Atsumi et al., “A Channel-Erasing 1.8-V-Only 32-Mb NOR Flash EEPROM with a Bitline Direct Sensing Scheme,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 11, November 2000, the teachings of which are incorporated herein by reference.
The configuration of FIG. 1C, which is presented by Antonino Conte et al., “A High-Performance Very Low-Voltage Current Sense Amplifier for Nonvolatile Memories,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 2, February 2005, the teachings of which are incorporated herein by reference, can achieve operation at a 1V power supply level. This configuration uses differential current-mode sensing and a folded-cascode amplifier to keep voltage swings small. It employs multiple re-charge boosting circuits to improve access time. However, it allows memory cell voltage to vary in direct proportion to transistor thresholds, reducing its suitability for tightly constrained flash technologies. Furthermore, its relatively large area and relatively high current consumption make it impractical for applications requiring a large number of sense amplifiers at low cost and low power.